е^.,(тах) = -eNXdr - -/2е^,Ма(2ф]р) (11.69) When Vsb > 0, the space charge width increases and we now have

QsD = -eNaXa = -г^ЖЩ+У^) (11-70) The change in the space charge density is then

To reach the threshold condition, the applied gate voltage must be increased. The change in threshold voltage can be written as

(11.7;

where AVj = Vf{Vse > 0) - VriVsB = 0)- We may note that Vsb tnust always be positive so that, for the n-channel device, AVr is always positive. The threshold voltage of the n-channel MOSFET will increase as a function of the source-substrate junction voltage.

EXAMPLE 11Л0 Objective

To calculate the change in the threshold voltage due to an applied source-to-body voltage.

Consider an n-channel silicon MOSFET at Г = 300 К. Assume the substrate is doped to JVa = 3 X 10 cm~ and assume the oxide is silicon dioxide with a thickness of = 500 A. Let V = 1 V.

Solution

We can calculate that

/N,\ / 3 x 10 \

ФГ, = V, in ( ) = (0.0259) in [jjj - 0.376 V

energy than are the electrons in the source. The newly created electrons will move laterally and flow out of the source terminal. When ф., - 2ф1р -F Vj, the surfac reaches an equilibrium inversion condition. The energy-band diagram for this condM tion is shown in Figure 11.51 c. The curve represented as Ef is the Fermi level froi the p substrate through the reverse-biased source-substrate junction to the source contact.

The space charge region width under the oxide increases from the original х^т value when a reverse-biased source-substrate junction voltage is applied. With applied Vsb > 0, there is more charge associated with this region. Considering the charge neutrality condition through the MOS structure, the positive charge on the top metal gate must increase to compensate for the increased negative space charge in order to reach the threshold inversion point. So when Vsb > 0, the threshold vohage of the n-channel MOSFET increases.

When Vsb =0, we had

0 I 1 2 0.64 13 2.19

V(js (volts)

Figure 11.521 Plots of л/Ь versus Vcs at several values of Vsb for ал n-channel MOSFET

We can also find

(3.9)(8.85 X 10)

500 X 10

= 6.9 X 10** F/cm-

Then from Equation (11.72), we can obtain

AVt =

[2(1.6 X 10 )(11.7)(8.85 X lQ--)(3 x 10 )l

6.9 x 10-

x ([2(0.376) + 1] - [2(0,376)]}

AVr 1,445(1.324 - 0.867) = 0,66 V

Comment

Figure 11,52 shows plots of VI о (sat) versus Vcs for various values of applied Vsb The original threshold voltage, V70, is 0.64 У

If a body or substrate bias is applied to a p-channel device, the threshold voltage is shifted to more negarive values. Because the threshold voltage of a p-channel enhancement mode MOSFET is negative, a body voltage will increase the applied negative gate vohage required to create inversion. The same general observation was made for the n-channel MOSFET.

EU.17

TEST YOUR UNDERSTANDING

A silicon MOS device has the following parameters: = cm~ and fox = 200 A. Calculate (a) the body-effect coefficient and (b) the change in threshold voltage for (0 Vsb = 1 V and (ii) Vsb =2\. IA 6930 = M V ( ) A 9Я10= M V Q) (Ф -j\A £€£ 0 = () sv]

Ell Л 8 Repeat exercise ЕП Л 7 for a substrate impurity doping concentration of lOm l LA 88800 = 0/) A ZSOO = V (.0 (<?) /гЛ eOIO = W si

11.4 I FREQUENCY LIMITATIONS

In many applications, the MOSFET is used in a linear amplifier circuit. A small-sigi equivalent circuit for the MOSFET is needed in order to mathematically analyze th electronic circuit. The equivalent circuit contains capacitances and resistances introduce frequency effects- We will inirially develop a small-signal equivalent circ and then discuss the physical factors that limit the frequency response of MOSFET. A transistor cutoff frequency, which is a figure of merit, will then be defii and an expression derived for this factor.

11-4Л Small-Signal Equivalent Circuit

The small-signal equivalent circuit of the MOSFET is constructed from the basi* MOSFET geometry. A model based on the inherent capacitances and resistanc within the transistor structure, along with elements that represent the basic devi( equations, is shown in Figure 11.53. One simplifying assumption we will make in th( equivalent circuit is that the source and substrate are both tied to ground potential.

Two of the capacitances connected to the gate are inherent in the device. These capacitances are Cgs and Cj, which represent the interaction between the gate and the channel charge near the source and drain terminals, respectively. The remaining two gate capacitances, Cgp and Cdp. are parasitic or overlap capacitances. In real devices, the gate oxide will overlap the source and drain contacts because of tolerance or fabrication factors. As we will see, the drain overlap capacitance-Сф, in particular-will lower the frequency response of the device. The parameter Cds is the

с

Figure 11.53 I Inherent resistances and capacitances in the n-channel MOSFET structure.

11-4 Frequency Limitations

drain-to-substrate pn junction capacitance, and and are the series resistances associated with the source and drain terminals. The small-signal channel current is con trolled by the internal gate-to-source voltage through the transconductance.

The small-signal equivalent circuit for the n-channe! common-source MOSFET is shown in Figure 11.54. The voltage V is the internal gate-to-source voltage that controls the channel current. The parameters С^т and Cgj *ire the total gate-to-source and total gate-to-drain capacitances. One parameter, л^, shown in Figure П.54, is not shown in Figure 11.53. This resistance is associated with the slope If) versus VdS the ideal MOSFET biased in the saturation region, is independent of Vps so that rj would be infinite. In short-channel-length devices, in particular, rs is finite because of channel length modulation, which we will consider in the next chapter.

A simplified small-signal equivalent circuit valid at low frequency is shown in Figure 11.55. The series resistances, r, and r,/, have been neglected, so the drain current is essentially only a function of the gate-to-source voltage through the transconductance. The input gate impedance is infinite in this simplified model.

The source resistance can have a significant effect on the transistor characterisfics. Figure 11.56 shows a simplified, low-frequency equivalent circuit including but neglecting rs* The drain current is given by

hi g

(11.73)

Figure IE54 I Small-signal equivalent circuit of a common-source n-channel MOSFET.

Figure 11.55 I Simplified, low-frequency small-signal equivalent circuit of a common-source n-channel MOSFET.

Figure 11.56 I SimpHfied, low-frequency small-signal equivalent circuit of common-source n-channel MOSFET including source resistance r,.

and the relation between V,v and V can be found from

The drain current from Equation (11.73) can now be written as

\ V - V

(11-74)

(1F75)

The source resistance reduces the effective transconductance or transistor gain.

The equivalent circuit of the p-channel MOSFET is exactly the same as that of the n-channel except that all voltage polarities and current directions are reversed. The same capacitances and resistances that are in the n-channel model apply to the p-channel model.

11,4.2 Frequency Limitation Factors and CutotTf Frequency

There are two basic frequency limitation factors in the MOSFET. The first factor is the channel transit time. Tf we assume that carriers are traveling at their saturation drift velocity i;, then the transit time is Т; - t/tsai where L is the channel length. If isat = 10 cm/s and L - 1 /лт, then Zf = 10 ps, which translates into a maximum frequency of 100 GHz. This frequency is much larger than the typical maximum frequency response of a MOSFET. The transit time of carriers through the channel is usually not the limiting factor in the frequency responses of MOSFETs.

The second limiting factor is the gate or capacitatice charging time. If we neglect rv, r, r and Cs, the resulting equivalent small-signal circuit is shown in Figure 11.57 where /?l is a load resistance.

The input gate impedance in this equivalent circuit is no longer infinite. Summing currents at the input gate node, we have

(И.76)

11-4 Frequency Limitations

Figure 11.57 I High-frequency small-signal equivalent circuit of common-source n-channel MOSFET.

Figure 11.58 I Small-signal equivalent circuit including Miller capacitance.

where /, is the input current. Likewise, summing currents at the output drain node, we have

(11.77)

Combining Equations (11.76) and (11.77) to eliminate the voltage variable V,, we can determine the input current as

1 + gm

I -i- jcoRiCdT J

(11.78)

Normally, wRiCjj is inuch less than unity; therefore we may neglect the (joyRiCgjr) term in the denominator. Equation (11.78) then simplifies to

Л = MQvr + (I -gmRL)]Vss

(11-79)

Figure 11.58 shows die equivalent circuit with the equivalent input impedance described by Equation (11.79), The parameter Сis the Miller capacitance and is given by

СM = CdT ( 1 + gm Rl)

(1L80)

The serious effect of the drain overlap capacitance now becomes apparent. When the transistor is operating in the saturation region, C essentially becomes zero, but Cgdp is a constant. This parasitic capacitance is multiplied by the gain of the transistor and can become a significant factor in the input impedance.

The cutoff frequency fj is defined to be the frequency at which the magnitude of the current gain of the device is unity, or when the magnitude of the input current is equal to the ideal load current Д/. From Figure 11.58, we can see that

and the ideal load current is

Id gm Vg, The magnitude of the current gain is then

(11-82)

к

27tf{C T + Cm)

(11.83)

Setting the magnitude of the current gain equal to unity at the cutoff frequency, find

where Cq is the equivalent input gate capacitance.

In the ideal MOSFET, the overlap or parasitic capacitances, Csp and Cp. zero. Also, when the transistor is biased in the saturation region, C approaches zero and is approximately CWL. The transconductance of the ideal MOSFET biased in the saturation region and assuming a constant mobility was given by Equa- tion (11.68) as

Then, for this ideal case, the cutoff frequency is

-[<ycs - Vt) y)

IttCg

(ПЯ5У

EXAMPLE 11.11

Objective

To calculate the cutoff frequency of an ideal MOSFET with a constant mobility.

Assume that the electron mobility in an n-channel device is д„ = 400 cnr/V-s and that the channel length is L = 4 дт. Also assume that VV = 1 V and let Vcs = 3 V.

Solution

From Equation (11.85), the cutoff frequency is

PniVcs-Vj) 400(3- 1)

2л

27г(4 x 10--*)

= 796 MHz

Comment

In an actual MOSFET, the effect of the parasitic capacitance will substantially reduce the cutoff frequency from that calculated in this example.

TEST YOUR UNDERSTANDING

E1L19 An n-channel MOSFET has the following parameters: = 400 cm/V-s, / - 200 A,W/L = 20, and Vt - 0.4 V. The transistor is biased at Vcs 2.5 V in the saturation region and is connected to an effective load of Rt = 100 kfi. Calculate the ratio of Miller capachance С л/ to gate-to-drain capacitance С^т- bZ suy)

El 1.20 An n-channel MOSFET has the same parameters as described in E11.19. The

channel length is L = 0.5 fim. Determine the cutoff frequency. (HD snv)

*11.5 I THE CMOS TECHNOLOGY

The primary objecrive of this text is to present the basic physics of semiconductor materials and devices without considering in detail the various fabricarion processes; this important subject is left to other texts. However, there is one MOS technology that is used extensively, for which the basic fabrication techniques must be considered in order to understand essential characterisrics of these devices and circuits. The one MOS technology we will consider briefly is the complementaiy MOS, or CMOS, process.

We have considered the physics of both n-channel and p-channel enhancement mode MOSFETs. Both devices are used in a CMOS inverter, which is the basis of CMOS digital logic circuits. The dc power dissipation in a digital circuit can be reduced to very low levels by using a complementary p-channel and n-channel pair.

It is necessary to form electrically isolated p- and n-substrate regions in an integrated circuit to accommodate the n- and p-channel transistors. The p-well process has been a commonly used technique for CMOS circuits. The process starts with a fairly low doped n-type silicon substrate in which the p-channel MOSFET will be fabricated. A diffused p-region, called a p well, is formed in which the n-channel MOSFET will be fabricated. In most cases, the p-type substrate doping level must be larger than the n-type substrate doping level to obtain the desired threshold voltages. The larger p doping can easily compensate the initial n doping to form the p well, A simplified cross section of the p-well CMOS structure is shown in Figure } 1.59a, The

Poly-Si gate

Poly-Si gate

n substrate

p substrate

Poly-Si gate

p or n substrate

Figure 11.59 I CMOS structures: (a) p well, (b) n well, and (c) twin well,

(fmmYmg[2/l.)

notation FOX stands for field oxide, which is a relatively thick oxide separating t devices. The field oxide prevents either the n or p substrate from becoming inverted and helps maintain isolation between the two devices. In practice, additional processing steps must be included; for example, providing connections so that p well and n substrate can be electrically connected to the appropriate voltages, n substrate must always be at a higher potential than the p well; therefore, this p junction will always be reverse biased.

With ion implantation now being extensively used for threshold voltage control, both the n-well CMOS process and twin-well CMOS process can be used. The n-well CMOS process, shown in Figure 11.59b, starts with an optimized p-type substrate that is used to form the n-channel MOSFETs. (The n-channel MOSFETs, in general, have superior characteristics, so this starting point should yield excellent n-channel devices.) The n well is then added, in which the p-channel devices are fabricated. The n-well doping can be controlled by ion implantation.

The twin-well CMOS process, shown in Figure 11.59c, allows both the p-well n-well regions to be optimally doped to control the threshold voltage and transconductance of each transistor. The twin-well process allows a higher packing density because of self-aligned channel stops.

One major problem in CMOS circuits has been latch-up. Latch-up refers to a high-current, low-voltage condition that may occur in a four-layer pnpn structure. Figure \ 1.60a shows the circuit of a CMOS inverter and Figure 11.60b shows a simplified integrated circuit layout of the inverter circuit. In the CMOS layout, the p-soun to n-substrate to p-well to n+-source forms such a four-layer structure.

The equivalent circuit of this four-layer structure is shown in Figure 11.61. The silicon controlled rectifier action involves the interaction of the parasitic pnp and npn transistors. The npn transistor corresponds to the vertical n source to p well to n substrate structure and the pnp transistor corresponds to the lateral p-well to n-substrate to p-source structure. Under normal CMOS operation, both parasitic bipolar transistors are cut off. However, under certain conditions, avalanche breakdown may occur in the p-well to n-substrate junction, driving both bipolar transistors into saturation. This high-current, low-voltage condition-latch-up-can sustain itself by

pii-

Input

p channel

Output

n channel

Input

Output

p well

n substrate

Figure 1L60 I (a) CMOS inverter circuit, (b) Simplified integrated circuit cross section of CMOS inverter

11.6 Summary

О

Figure J1.6J 1 (a) The spJitting of the basic pnpn structure, (b) The two-transistor equivalent circuit of the four-layered pnpn device.

positive feedback. The condition can prevent the CMOS circuit from operating and can also cause permanent damage and burn-out of the circuit.

Latch-up can be prevented if the product фр is less than unity at all times, where and are the common-emitter current gains of the npn and pnp parasitic bipolar transistors, respectively. One method of preventing latch-up is to kilf the minority carrier lifetime. Minority carrier lifetime degradation can be accomplished by gold doping or neutron irradiation, either of which introduces deep traps within the semiconductor. The deep traps increase the excess minority carrier recombination rate and reduce current gain. A second method of prevenring latch-up is by using proper circuit layout techniques. If the two bipolar transistors can be effecrively decoupled, then latch-up can be minimized or prevented. The two parasitic bipolar transistors can also be decoupled by using a different fabrication technology. The silicon-on-insulator technology, for example, allows the n-channel and the p-channel MOSFETs to be isolated from each other by an insulator. This isolation decouples the parasitic bipolar transistors.

1L6 I SUMMARY

The fundamental physics and characteristics of the metal-oxide-semiconductor field-effect transistor (MOSFET) have been considered in this chapter.

The heart of the MOSFET is the MOS capacitor. The energy bands in the semiconductor adjacent to the oxide-semiconductor interface bend, depending upon the voltage applied across the MOS capacitor The position of the conduction and valence bands relative to the Fermi level at the surface is a function of the MOS capacitor voltage.

The semiconductor suriace at the oxide-semiconductor interface can be inverted from

p type to n type by applying a positive gate voltage, or from n type to p type by applying