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inductance within the module. Reducing the parasitic inductance reduces the high-frequency ringing during transients that is another cause of radiated electromagnetic interference, as since stray inductance can cause large peak vohages during switching transients, minimizing it helps to maintain the device within its safe operating area.
Long life and high reliability are primarily attained through minimization of thermal cychng, minimization of ambient temperature, and proper design of the transistor stack. Thermal cycling fatigues material interfaces because of coefficient of thermal expansion (CTE) mismatch between dissimilar materials. As the materials undergo temperature variation, they expand and contract at different rates, which stresses the interface between the layers and can cause interface deterioration (e.g., cracking of solder layers or wire debonding). Chemical degradation processes such as dendrite growth and impurity migration are accelerated with increasing temperature, so keeping the absolute temperature of the device low and minimizing the temperature changes to which it is subject are important. Typical CTE values for common package materials are given in Table 3.2.
Low cost is achieved in a variety of ways. Both manufacturing and material costs must be taken into account when designing a power module. Materials that are difficult to machine or form, even if they are relatively cheap in raw form, molybdenum, for example, should be avoided. Manufacturing processes that lower yield also drive up costs. In addition, a part that is very rehable can reduce future costs by reducing the need for repair and replacement.
The basic half-bridge module has three power terminals: plus, minus, and phase. Advanced modules differ from traditional high-power commercial modules in several ways. The baseplate is metallized aluminum nitride (AIN) ceramic rather than the typical 0.25-thick, nickel-plated copper baseplate with a soldered metallized ceramic substrate for electrical isolation. This AlN baseplate stack provides a low thermal resistance from die to heat sink. The copper terminal power buses are attached by solder to the devices in a wirebond-free, low-inductance, low-resistance, device-interconnect configuration. The balance of the assembly is typical for module
table 3.2 CTE for thyristor package materials
figure 3.7 Advanced module cut-away showing contacts without using wirebonds.
manufacturing with attachment of shells, use of dielectric gels, and with hard epoxies and adhesives to seal the finished module. An example of an advanced module is shown in Fig. 3.7. Details of the thermal performance of modules and advanced modules can be found in Beker et al.  and Godbold etal. .
3.4 Dynamic Switching Characteristics
The time rate of rise of both anode current (di/dt) during turn-on and anode-cathode voltage (dv/dt) during turn-off is an important parameter to control for ensuring proper and reliable operation. All thyristors have maximum limits for di/dt and dv/dt that must not be exceeded. Devices capable of conducting large currents in the on-state are necessarily made with large-surface areas through which the current flows. During turn-on, localized areas (near the gate region) of a device begin to conduct current. The initial turn-on of an SCR is shown in Fig. 3.8. The cross section illustrates how injected gate current flows to the nearest cathode region, causing this portion of the npn transistor to begin conducting. The pnp transistor then follows the npn into conduction such that
С OSS s ction
figure 3.8 Top view and associated cross section of gate-cathode periphery showing initial turn-on region in a center-fired thyristor.
anode current begins flowing only in a small portion of the cathode region. If the local current density becomes too large (in excess of several thousand amperes per square centimeter), then self-heating will damage the device. Sufficient time (referred to as plasma spreading time) must be allowed for the entire cathode area to begin conducting before the localized currents become too high. This phenomenon results in a maximum allowable rate of rise of anode current in a thyristor and is referred to as a di/dt limit. In many high-frequency applications, the entire cathode region is never fully in conduction. Prevention of di/dt failure can be accomplished if the rate of increase of the conduction area exceeds the di/dt rate such that the internal junction temperature does not exceed a specified critical temperature (typically 350 °C). This critical temperature decreases as the blocking voltage increases. Adding series inductance to the thyristor to limit di/dt below its maximum usually causes circuit design problems.
Another way to increase the di/ dt rating of a device is to increase the amount of gate-cathode periphery. Inverter SCRs
figure 3.9 Top view of typical interdigitated gate-cathode patterns used for thyristors.
(so named because of their use in high-frequency power converter circuits that convert dc to ac - invert) are designed so that there is a large amount of gate edge adjacent to a significant amount of cathode edge. A top surface view of two typical gate-cathode patterns, found in large thyristors is shown in Fig. 3.9. An inverter SCR often has a stated maximum di/dt limit of 2000A/is. This value has been shown to be conservative , and by using excessive gate current under certain operating conditions, an inverter SCR can be operated reliably at 10,000 to 20,000 A/is.
A GTO takes the interdigitation of the gate and cathode to the extreme (Fig. 3.9, left). In Fig. 3.10 a cross section of a GTO shows the amount of interdigitation. A GTO often has cathode islands that are formed by etching the Si. A metal plate can be placed on the top to connect the individual cathodes into a large arrangement of electrically parallel cathodes. The gate metallization is placed so that the gate surrounding each cathode is electrically in parallel as well. This construction not only allows high di/dt values to be reached, as in an inverter SCR, but also provides the capability to turn off the anode current by shunting it away from the individual cathodes and out the gate electrode upon reverse-biasing of the gate. During turn-off, current is decreasing while voltage across the device is increasing. If the forward voltage becomes too high while sufficient current is still flowing, then the device will drop back into its conduction mode instead of
figure 3.10 Cross section of a GTO showing the cathode islands and interdigitation with the gate (/>-base).
completing its turn-off cycle. Also, during turn-off, the power dissipation can become excessive if the current and voltage are simultaneously too large. Both of these turn-off problems can damage the device as well as other portions of the circuit.
Another switching problem that occurs is associated primarily with thyristors, although other power electronic devices suffer some degradation of performance from the same problem. This problem occurs because thyristors can self-trigger into a forward-conduction mode from a forward-blocking mode if the rate of rise of forward anode-cathode voltage is too large. This triggering method is due to displacement current through the associated junction capacitances (capacitance at /2 dominates because it is reverse-biased under forward applied voltage). The displacement current contributes to the leakage current shown in Eq. (1). Therefore SCRs and CTOs have a maximum dv/dt rating that should not be exceeded (typical values are 100 to 1000 V/is). Switching into a reverse-conducting state from a reverse-bioeking state due to an applied reverse dv/dt, is not possible because the values of the reverse as of the equivalent transistors can never be made large enough to cause the necessary feedback (latching) effect. An external capacitor is often placed between the anode and cathode of the thyristor to help control the dv/dt experienced. Capacitors and other components that are used to form such protection circuits, known as snubbers, are used with all power semiconductor devices.
3.4.1 Cathode Shorts
As the temperature in the thyristor increases >25°C, the minority carrier hfetime and the corresponding diffusion lengths in the n- and p-bases increase. This leads to an increase in the as of the equivalent transistors. Discussion of the details of the minority carrier diffusion length and its role in determining the current gain factor a can be found in Sze . Referring to Eq. (1), it is seen that a lower applied bias will give a carrier multiplication factor M, sufficient to switch the device from forward-blocking into conduction because of this increase of the as with increasing temperature. Placing a shunt resistor in parallel with the base-emitter junction of the
figure 3.12 Cross section showing cathode shorts and the resulting resistive shunt path for anode current.
equivalent npn transistor (shown in Fig. 3.11) will result in an effective current gain aeff that is lower than a , as given by Eq. (2), where Vq is the applied gate-cathode voltage, is the equivalent lumped value for the distributed current shunting structure, and the remaining factors form the appropriate current factor based on the applied bias and characteristics of the gate-cathode junction. The shunt current path is implemented by providing intermittent shorts, called cathode shorts, between the p-base (gate) region and the /7+-emitter (cathode) region in the thyristor as illustrated in Fig. 3.12. The lumped shunt resistance value is in the range of 1 to 15 Q as measured from gate to cathode.
---\l + VaKJRsioeo./kT
figure 3.11 Two-transistor equivalent circuit showing the addition of a resistive shunt path for anode current.
Low values of anode current (e.g., those associated with an increase in temperature under forward-blocking conditions) will flow through the shunt path to the cathode contact, bypassing the /7+-emitter and keeping the device out of its forward-conduction mode. As the anode current becomes large, the potential drop across the shunt resistance will be sufficient to forward bias the gate-cathode junction /3 and bring the thyristor into forward conduction. The cathode shorts also provide a path for displacement current to flow without forward biasing /3. Both the dv/dt rating of the thyristor and the forward blocking characteristics are improved by using cathode shorts. However, the shorts do, cause a lowering of cathode current handhng capability because of the loss of some of the cathode area (/7+-region) to the shorting pattern, an increase in the necessary gate current to obtain switching from forward-blocking to forward-conduction, and an increased complexity in manufacturing the thyristor. The loss of cathode area due to the shorting-structure is from 5 to 20%, depending on the type of thyristor. By careful design of the cathode short windows to the p-base, the holding current can be made lower than the latching current. This is important
figure 3.13 Cross section showing integrated cathode and anode shorts.
SO that the thyristor will remain in forward conduction when used with varying load impedances.
3.4.2 Anode Shorts
A further increase in forward-blocking capability can be obtained by introducing anode shorts (reduces dp in a similar manner that cathode shorts reduce a ) along with the cathode shorts. An illustration of this is provided in Fig. 3.13. In this structure, both and /3 are shorted (anode and cathode shorts) so that the forward-blocking capability of the thyristor is completely determined by the avalanche breakdown characteristics of /2. Anode shorts will result in the complete loss of reverse-blocking capability and is only for thyristors used in asymmetric circuit applications.
3.4.3 Amplifying Gate
The cathode-shorting structure will reduce the gate sensitivity dramatically. To increase this sensitivity and yet retain the benefits of the cathode-shorts, a structure called an amplifying gate (or regenerative gate) is used, as shown in Fig. 3.14 (and
AmpHfying Pilot gate gate contact
Cross section showing the amplifying gate structure in a
Fig. 3.9, right). When the gate current (1) is injected into the p-base through the pilot-gate contact, electrons are injected into the p-base by the /7+-emitter with a given emitter injection efficiency. These electrons traverse through the p-base (time taken for this process is called the transit time) and accumulate near the depletion region. This negative charge accumulation leads to injection of holes from the anode. The device then turns-on after a certain delay, dictated by the p-base transit time, and the pilot anode current (2 on the figure) begins to flow through a small region near the pilot-gate contact as shown in Fig. 3.14.
This flow of pilot anode current corresponds to the initial sharp rise in the anode current waveform (phase I), as shown in Fig. 3.15. The device switching then goes into phase II, during which the anode current remains fairly constant, suggesting that the resistance of the region has reached its lower limit. This is due to the fact that the pilot anode current (2) takes a finite time to traverse through the p-base laterally and become the gate current for the main cathode area. The /7+-emitters start to inject electrons which traverse the p-base vertically and after a certain finite time (transit time of the p-base) reach the depletion region. The total time taken by the lateral traversal of pilot anode current and the electron transit time across the p-base is the reason for observing this characteristic phase II interval. The width of the phase II interval is comparable to the switching delay, suggesting that the p-base transit time is of primary importance. Once the main cathode region turns on, the resistance of the device decreases and the anode current begins to rise again (transition from phase II to phase III). From this time onward in the switching cycle, the plasma spreading velocity will dictate the rate at which the conduction area will increase. The current density during phase I and phase II can be quite large, leading to a considerable increase in the local temperature and device failure. The detailed effect of the amplifying gate on the anode current rise will be noticed only at high levels of di/dt (in the range of 1000A/is). It can be concluded that the amplifying gate will increase gate sensitivity at the expense of some di/dt capability, as demonstrated by Sankaran et al. (8). This
Vk 500 V/divisior
figure 3.15 Turn-on waveforms showing the effect of the amplifying gate in the anode current rise.
lowering of di/dt capability can be somewhat offset by an increase in gate-cathode interdigitation as previously discussed.
3.4.4 Temperature Dependencies
The forward blocking voltage of an SCR has been shown to be reduced from 1350 V at 25 °C to 950 V at -175 °C in a near linear fashion . Above 25 °C, the forward-blocking capability is again reduced due to changes in the minority carrier lifetime. Several dominant physical parameters associated with semiconductor devices are sensitive to temperature variations, causing their dependent device characteristics to change dramatically. The most important of these parameters are: i) the minority carrier lifetimes (which control the high-level injection lifetimes); ii) the hole and electron mobilities; Hi) the impact ionization collision cross sections; and iv) the free-carrier concentrations (primarily the ionized impurity-atom concentration). Almost all of the impurity atoms are ionized at temperatures >0°C, and so further discussion of the temperature effects on ionization is not relevant for normal operation. The detailed discussion of these physical parameters is beyond the scope of this chapter but references listed for those interested in pursuing relevant information about temperature effects.
It is well known that charge carrier recombination events are more efficient at lower temperatures. This shows up as a larger potential drop during forward conduction and a shorter recovery time during turn-off. A plot of the anode current during turn-off, at various temperatures, for a typical СТО is shown in Fig. 3.16.
An approximate relation between the temperature and the forward drop across the n-base of a thyristor is discussed in detail by Herlet  and Hudgins et al. . The junction potential drops in the device, the temperature dependence of the bandgap energy, along with the n-base potential drop, a
temperature-dependent equation relating anode current density /д, and the applied anode-cathode voltage V are also given in Reference . Data from measurements at forward current densities 100 A/cm on a СТО rated for 1-kV symmetric blocking have forward voltage drops of 1.7 V at -50°C to 1.8 V at 150 °C.
3.5 Thyristor Parameters
Understanding of a thyristors maximum ratings and electrical characteristics is required for proper apphcation. Use of a manufacturers data sheet is essential for good design practice. Ratings are maximum or minimum values that set limits on device capability. A measure of device performance under specified operating conditions is a characteristic of the device. A summary of some of the maximum ratings that must be considered when choosing a thyristor for a given application is provided in Table 3.3. Thyristor types shown in parentheses indicate a maximum rating unique to that device. Both forward and reverse repetitive and nonrepetitive voltage ratings must be considered, and a properly rated device must be chosen so that the maximum voltage ratings are never exceeded. In most cases, either forward or reverse voltage transients in excess of the nonrepetitive maximum ratings result in destruction of the device. The maximum rms or
Temperature effect on the anode current tail during
average current ratings given are usually those that cause the junction to reach its maximum rated temperature. Because the maximum current will depend upon the current waveform and upon thermal conditions external to the device, the rating is usually shown as a function of case temperature and conduction angle. The peak single half-cycle surge-current rating must be considered, and in applications where the thyristor must be protected from damage by overloads, a fuse with an It rating smaller than the maximum rated value for the device must be used. Maximum ratings for both forward and reverse gate voltage, current, and power also must not be exceeded.
The maximum rated operating junction temperature Tj must not be exceeded, as device performance, in particular voltage-blocking capability, will be degraded. Junction temperature cannot be measured directly but must be calculated from a knowledge of steady-state thermal resistance R@Q-cy the average power dissipation. For transients or surges, the transient thermal impedance (Z(q q curve must be used (provided in manufacturers data sheets). The maximum average power dissipation Pj is related to the maximum rated operating junction temperature and the case temperature by the steady-state thermal resistance. In general, both maximum dissipation and its derating with increasing case temperature are provided.
The number and type of thyristor characteristics specified varies widely from one manufacturer to another. Some characteristics are given only as typical values of minima or maxima, while many characteristics are displayed graphically. Table 3.4 summarizes some of the typical characteristics provided as maximum values. The maximum value means that the manufacturer guarantees that the device will not exceed the value given under the specified operating or switching conditions. A minimum value means that the manufacturer guarantees that the device will perform at least as good as the characteristic given under the specified operating or switching conditions. Thyristor types shown in parentheses indicate a characteristic unique to that device. Gate conditions of both voltage and current to ensure either nontriggered or triggered device operation are included. The turn-on and turn-off transients of the thyristor are characterized by switching times like the turn-off time listed in Table 3.4. The turn-on transient can be divided into three intervals: i) gate-delay interval; ii) turn-on of initial area; and iii) spreading interval. The gate-delay interval is simply the time between application of a turn-on pulse at the gate and the time the initial cathode area turns on. This delay decreases with increasing gate drive current and is of the order of a few microseconds. The second interval, the time required for turn-on of the initial area, is quite short, typically < 1 is. In general, the initial area turned on is a small percentage of the total useful device area. After the initial area turns on, conduction spreads (spreading interval or plasma spreading time) throughout the device in tens of microseconds for high-
table 3.4 Typical thyristor characteristic maximums and minimum specified by manufacturers
Maximum on-state voltage drop (at specified junction
temperature and forward current) Maximum forward off-state current (at specified junction
temperature and forward voltage) Maximum reverse off-state current (at specified junction
temperature and reverse voltage) Minimum critical rate of rise of off-state voltage at
specified junction temperature and forward-blocking
Maximum gate trigger voltage (at specified temperature and
forward applied voltage) Maximum gate nontrigger voltage (at specified temperature
and forward appHed voltage) Maximum gate trigger current (at specified temperature
and forward appHed voltage) Maximum turn-on time (under specified switching
Maximum turn-off time (under specified switching conditions)
Maximum turn-on delay time (for specified test) Maximum junction-to-case thermal resistance Maximum case-to-sink thermal resistance (interface lubricated)
speed devices or thyristors. The plasma spreading time may take up to hundreds of microseconds in large-area phase-control devices.
Table 3.5 lists many of the thyristor parameters that appear either as listed values or as information on graphs. The definition of each parameter and the test conditions under which they are measured are given in the table as well.
3.6 Types of Thyristors
In recent years, most development effort has gone into both continued integration of the gating and control electronics into thyristor modules and the use of MOS technology to create gate structures integrated into the thyristor itself. Many variations of this theme are being developed and some technologies should rise above the others in the years to come. Further details concerning most of the following discussion of thyristor types can be found in Reference [ 1 ].
3.6.1 SCRs and GTOs
The highest power handling devices continue to be bipolar thyristors. High-powered thyristors are large diameter devices, some well in excess of 100 mm, and as such have a limitation on the rate of rise of anode current, a di/dt rating. The depletion capacitances around the pn junctions, in particular the center junction, limit the rate of rise in forward voltage that can be applied even after all the stored charge, introduced
table 3.5 Symbols and definitions of major thyristor parameters
Ts Tc Tj
thermal resistance Junction-to-case thermal
resistance Junction-to-sink thermal
resistance Contact thermal
resistance Transient thermal
impedance Junction-to-case transient
thermal impedance Junction-to-sink
impedance Ambient temperature
Sink temperature Case temperature Junction temperature
Storage temperature Peak reverse blocking
voltage Transient peak reverse
blocking voltage DC Reverse blocking
voltage Peak forward blocking
Transient peak forward blocking voltage
DC Forward blocking voltage
Critical rate-of-rise of off-state voltage dv/dt = (0.632 F))/t Vj is specified off-state voltage t is time constant for exponential
Peak on-state voltage
RMS on-state current Average on-state current
Peak on-state current
Specifies the degree of temperature rise per unit of power, measuring junction temperature from a
specified external point. Defined when junction power dissipation results in steady-state thermal flow. The steady-state thermal resistance between the junction and ambient.
The steady-state thermal resistance between the junction and case surface.
The steady-state thermal resistance between the junction and the heat sink mounting surface.
The steady-state thermal resistance between the surface of the case and the heat sink mounting surface.
The change of temperature difference between two specified points or regions at the end of a time
interval divided by the step function change in power dissipation at the beginning of the same interval causing the change of temperature difference.
The transient thermal impedance between the junction and ambient.
The transient thermal impedance between the junction and the case surface.
The transient thermal impedance between the junction and the heat sink mounting surface.
It is the temperature of the surrounding atmosphere of a device when natural or forced-air cooling is
used, and is not influenced by heat dissipation of the device. The temperature at a specified point on the device heat sink. The temperature at a specified point on the device case.
The device junction temperature rating. Specifies the maximum and minimum allowable operation temperatures.
Specifies the maximum and minimum allowable storage temperatures (with no electrical connections). Within the rated junction temperature range, and with the gate terminal op en-circuited, specifies the
repetitive peak reverse anode to cathode voltage applicable on each cycle. Within the rated junction temperature range, and with the gate terminal op en-circuited, specifies the
nonrepetitive peak reverse anode to cathode voltage applicable for a time width equivalent to < 5 ms. Within the rated junction temperature range, and with the gate terminal op en-circuited, specifies the
maximum value for dc anode to cathode voltage applicable in the reverse direction. Within the rated junction temperature range, and with the gate terminal op en-circuited (SCR), or with a
specified reverse voltage between the gate and cathode (GTO), specifies the repetitive peak off-state
anode to cathode voltage applicable on each cycle. This does not apply for transient off-state voltage
Within the rated junction temperature range, and with the gate terminal op en-circuited (SCR), or with a specified reverse voltage between the gate and cathode (GTO), specifies the nonrepetitive off-state anode to cathode voltage applicable for a time width equivalent to < 5 ms. This gives the maximum instantaneous value for nonrepetitive transient off-state voltage.
Within the rated junction temperature range, and with the gate terminal op en-circuited (SCR), or with a specified reverse voltage between the gate and cathode (GTO), specifies the maximum value for dc anode to cathode voltage applicable in the forward direction.
At the maximum rated junction temperature range, and with the gate terminal open-circuited (SCR), or with a specified reverse voltage between the gate and cathode (GTO), this specifies the maximum rate-of-rise of off-state voltage that will not drive the device from an off-state to an on-state when an exponential off-state voltage of specified amplitude is applied to the device.
At specified junction temperature, and when on-state current (50 or 60 Hz, half sine wave of specified peak amplitude) is applied to the device, indicates peak-value for the resulting voltage drop.
At specified case temperature, indicates the rms value for on-state current that can be continuously applied to the device.
At specified case temperature, and with the device connected to a resistive or inductive load, indicates the average value for forward-current (sine half wave, commercial frequency) that can be continuously applied to the device.
Within the rated junction temperature range, indicates the peak-value for non-repetitive on-state current (sine half wave, 50 or 60 Hz). This value indicated for one cycle, or as a function of a number of cycles.
table 3.5 (Continued)
The maximum, on-state, nonrepetitive short-time thermal capacity of the device and is helpful in selecting a fuse or providing a coordinated protection scheme of the device in the equipment. This rating is intended specifically for operation less than one half cycle of a 180° (degree) conduction angle sinusoidal waveform. The off-state blocking capability cannot be guaranteed at values near the maximum Pt.
At specified case temperature, specified off-state voltage, specified gate conditions, and at a frequency of < 60 Hz, indicates the maximum rate-of-rise of on-state current which the thyristor will withstand when switching from an off-state to an on-state, when using recommended gate drive.
At maximum rated junction temperature, indicates the peak value for reverse-current flow when a voltage (sine half wave, 50 or 60 Hz, and having a peak value as specified for repetitive peak reverse-voltage rating) is appHed in a reverse direction to the device.
At maximum rated junction temperature, indicates the peak-value for off-state-current flow when a voltage (sine half wave, 50 or 60 Hz, and having a peak value for repetitive off-state voltage rating) is appHed in a forward direction to the device. For a GTO, a reverse voltage between the gate and cathode is specified.
GTO Only qt GTO Only
Turn-on time Turn-off time
Within the rated junction temperature range, indicates the peak value for maximum aUowable power dissipation over a specified time period, when the device is in forward conduction between the gate and cathode.
Within the rated junction temperature range, indicates the average value for maximum aHowable power
dissipation when the device is forward-conducting between the gate and cathode. Within the rated junction temperature range, indicates the peak value for maximum aUowable power
dissipation in the reverse direction between the gate and cathode, over a specified time period. Within the rated junction temperature range, indicates the average value for maximum aHowable power
dissipation in the reverse direction between the gate and cathode. Within the rated junction temperature range, indicates the peak value for forward-current flow between
the gate and cathode.
Within the rated junction temperature range, indicates peak value for reverse-current that can be
conducted between the gate and cathode. Within the rated junction temperature range, indicates the peak value for reverse-voltage appHed between
the gate and cathode.
Within the rated junction temperature range, indicates the peak value for forward-voltage applied between the gate and cathode.
At a junction temperature of 25 °C, and with a specified off-voltage, and a specified load resistance, indicates the minimum gate dc current required to switch the thyristor from an off-state to an on-state.
At a junction temperature of 25 °C, and with a specified off-state voltage, and a specified load resistance, indicates the minimum dc gate voltage required to switch the thyristor from an off-state to an on-state.
At maximum rated junction temperature, and with a specified off-state voltage appHed to the device, indicates the maximum dc gate voltage that wiH not switch the device from an off-state to an on-state.
Under specified conditions, indicates the instantaneous value for on-current usable in gate control, specified immediately prior to device turn-off.
At specified junction temperature, and with a peak repetitive off-state voltage of half-rated value, foHowed by device turn-on using specified gate current, and when specified on-state current of specified di/dt flows, indicated as the time required for the applied off-state voltage to drop to 10% of its initial value after gate current application. Delay time is the term used to define the time required for applied voltage to drop to 90% of its initial value foHowing gate-current application. The time required for the voltage level to drop from 90% to 10% of its initial value is referred to as rise time. The sum of both of these defines turn-on time.
Specified at maximum rated junction temperature. Device set up to conduct on-state current, foHowed by applying specified reverse anode-cathode voltage to quench on-state current, and then increasing the anode-cathode voltage at a specified rate-of-rise as determined by circuit conditions controlHng the point where the specified off-state voltage is reached. Turn-off time defines the minimum time which the device wiH hold its off-state, starting from the time on-state current reached zero untH the time forward voltage is again appHed (i.e., applied anode-cathode voltage becomes positive again).
When applying forward-current to the gate, indicates the time required to switch the device from an off-state to an on-state.
When applying reverse-current to the gate, indicates the time required to switch the device from an on-state to an off-state.
during conduction, is removed. The associated displacement current under apphcation of forward voltage during the thyristor blocking state sets a dv/dt limit. Some effort in improving the voltage hold-off capability and overvoltage protection of conventional silicon-controlled rectifiers (SCRs) is underway by incorporating a lateral high-resistivity region to help dissipate the energy during break-over. Most effort, though, is being directed toward further development of high-performance gate turn-off (СТО) thyristors because of their controllability and to a lesser extent in optically triggered structures that feature gate circuit isolation.
High-voltage СТО thyristors with symmetric blocking capability require thick n-base regions to support the high electric field. The addition of an /7+-buffer layer next to the p+-anode allows high voltage blocking and a low forward voltage drop during conduction because of the thinner n-base required. Cylindrical anode shorts have been incorporated to facilitate excess carrier removal from the n-base during turn-off and still retain high blocking capability. This device structure can control 200 A, operating at 900 Hz, with a 6-kV hold-off. Some of the design trade-offs between the n-base width and turn-off energy losses in these structures been determined. A similar СТО incorporating an /7+-buffer layer and a pin structure has been fabricated that can control up to IkA (at a forward drop of 4V) with a forward blocking capability of 8 kV. A reverse-conducting СТО has been fabricated that can block 6 kV in the forward direction, interrupt a peak current of 3kA, and has a turn-off gain of 5.
A modified СТО structure, called a gate commutated thyristor (CCT), has been designed and manufactured that commutates all of the cathode current away from the cathode region and diverts it out the gate contact. The CCT is similar to a СТО in structure except that it has a low-loss n-buffer region between the n-base and p-emitter. The CCT device package is designed to result in very low parasitic inductance and is integrated with a specially designed gate-drive circuit. The specially designed gate drive and ring-gate package circuit allow the CCT to be operated without a snubber circuit and switch with higher anode di/dt, than a similar СТО. At blocking voltages of 4.5 kV and higher the CCT seems to provide better performance than a conventional СТО. The speed at which the cathode current is diverted to the gate (digq/dt) is directly related to the peak snubberless turn-off capability of the CCT. The gate drive circuit can sink current for turn-off at digq/dt values > 7000 A/is. This hard gate drive results in a low charge storage time of 1 is. Low storage time and fail-short mode make the CCT attractive for high-voltage series applications.
3.6.2 MOS-ControUed Thyristors, MCT
The corresponding equivalent circuit of the p-type MCT unit cell is provided in Fig. 3.17. When the MCT is in its forward blocking state and a negative gate-anode voltage is applied, an
figure 3.17 Cross section of unit-cell of a p-tjpe MCT.
inversion layer is formed in the n-doped material that allows holes to flow laterally from the p-emitter (p-channel FET source) through the channel to the p-base (p-channel FET drain). This hole flow is the base current for the npn transistor. The /7-emitter then injects electrons, which are collected in the /7-base, causing the p-emitter to inject holes into the n-base so that the pnp transistor is turned on and latches the MCT. The MCT is brought out of conduction by applying a positive gate-anode voltage. This signal creates an inversion layer that diverts electrons in the n-base away from the p-emitter and into the heavily doped n-region at the anode. This n-channel FET current amounts to a diversion of the pnp transistor base current so that its base-emitter junction turns off. Holes are then no longer available for collection by the p-base. The ehmination of this hole current (npn transistor base current) causes the npn transistor to turn off. The remaining stored charge recombines and returns the MCT to its blocking state. The seeming variability in fabrication of the turn-off FET structure continues to limit the performance of MCTs, particularly current interruption capability, although these devices can handle 2 to 5 times the conduction current density of ICBTs. Numerical modeling and experimental verification of the modeling have shown the sensitivity that an ensemble of cells has to current filamentation during turn-off. All MCT device designs center around the problem of current interrup-
tion capability. Both turn-on, which is relatively simple, by comparison, and conduction properties approach the one-dimensional (ID) thyristor limit.
Early generations of MCTs had > 50,000 cells connected in parallel. Newer devices have > 200,000 cells, with a total active area of 0.38 cm. These devices are rated for 1000 V and a peak controllable current of 75 A. All of the cells contain an n-channel FET structure to turn off, and 4% have the p-channel FET structure to turn the device on. The latest version of the standard MCT is a diffusion-doped (instead of the usual epitaxial growth) device with an active area of 1 cm. They are rated for 3000-V forward blocking, have a forward drop of 2.5 V at 100 A, and are capable of interrupting around 300 A with a recovery time of 5 is. Three of these high-voltage devices have been placed in a series array that operates at 5-kV blocking and interrupts 150 A. Other MCTs have been designed to withstand 2.5 kV with a turn-off capability of several kiloamperes per square centimeter per unit cell. Turn-off simulations have been performed for high-voltage MCTs as well as discussion of lateral device designs. A thorough analysis of the interaction of field plates and guard rings in punch-through and non-punch-through structures, for achieving high-voltage planar junctions has also been performed.
Trench- or buried-gate technology has contributed to the reduction of the R x Area product in power MOSFETs by a factor of three or more compared to surface gate devices. An MCT that uses this technology, called a depletion-mode thyristor (DMT), was designed. The cross section of the device and a simple equivalent circuit are shown in Fig. 3.18. The depletion region formed between the trench-gate fingers, by applying a negative gate-cathode voltage, diverts current away from the /7+-emitter (cathode) of the thyristor structure to the collector of a pnp transistor structure (also at the cathode) through a lateral resistance (the p-base of the thyristor). This current diversion turns off the equivalent npn transistor of the thyristor structure, thus depriving the thyristors pnp transistor of any base current and which results in complete turn-off of the device. Depletion mode thyristors were produced that had forward-blocking ratings of 500 V, 1.1 V forward drop at 200 A/cm (a similar IGBT had a forward drop of 2 V at the same current density), and could control a maximum current density of 5000 A/cm. A similar device is the base resistance controlled thyristor (BRT). Here, a p-channel MOSFET is integrated into the n-drift region of the MCT, and is used to modulate the lateral p-base resistance of the thyristor, causing the holding current to increase above the conduction value, thus achieving turn-off. Some BRTs were fabricated with 600-V blocking capability and an active area of 1.3 mm (315 cells). These devices operate in an IGBT mode until the current is large enough to cause the thyristor structure to latch. The forward drop was 1.24 V at 300A/cm, about the same as a similarly fabricated thyristor.
figure 3.18 Cross section and equivalent circuit for a depletion-mode thyristor (DMT).
Another new MCT structure has been demonstrated. Called an emitter switched thyristor (EST), it uses an integrated lateral MOSFET to connect a floating thyristor n-emitter region to an /7+-thyristor cathode region, as shown in Fig. 3.19. The lateral MOS structure is such that it can initially turn on the thyristors pnp transistor. When enough anode current flows, the p-base-/7-floating-emitter junction injects carriers and the thyristor latches (the EST moves from an IGBT-like operating mode to a latched thyristor mode). All thyristor current flows through the lateral MOSFET so that it can control the thyristor current. The gate can lose control if the thyristor current becomes excessive so that the parallel parasitic thyristor latches. The ESTs were designed for 600-V forward-blocking and can interrupt 1000 A/cm per unit cell with a turn-off time 7 is. Integrating an IGBT into a thyristor structure has been proposed. This device, called an IGBT-triggered thyristor (ITT), is similar in structure and operation to the EST. Two-dimensional (2D) simulations comparing switching of an inductive load and conduction performance of the ITT to a conventional IGBT have indicated
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