uating the cost and technical constraints, and then matching packaging technologies to the groupings. All this is set against a set of comprehensive user requirements.

35.3.1 Setting User Requirements

Effective systems design, including packaging, relies on accurate and comprehensive user requirements that are estabhshed through a formal structure. A brief review is presented here. The requirements are divided into five business taxonomies that can be considered comprehensive. These are: financial, environmental, legal, social and technical. The taxonomies are matrixed with three characteristics of requirements: assumed, articulated and unexpected. Assumed requirements are basic requirements for a product, process or service to be acceptable to aU end users. Articulated requirements discern one user from another. The unexpected requirements are exciters that make the product, process or service unique and competitive.

Of the above, only technical, articulated, user requirements are used in this discussion.

The technical requirements are further categorized to reflect the electrophysical nature of packaging. The categories are: chemical, electrical, magnetic, mechanical and thermal. Relating the requirements to aU relevant energy forms provides a comprehensive listing. The energy forms in this discussion are limited to electrical, magnetic, mechanical and thermal.

35.3.2 Steps To Partitioning

A first step to partitioning is the creation of a comprehensive categorized list of electrical, mechanical and thermal, technical user requirements. This is performed as mentioned above.

The second step is creation of a simple component characterization map that identifies dominant attributes of the components. The block diagram of a 2.2 kW motor drive is shown in Figure 35.1 and part of the characterization map is given in Table 35.1 The map is divided into metrics by energy

TABLE 35.1 Component characterization map

form to categorize and record extreme operating values for each component. Not all blocks need to be completed or components included, only those that most impact the technology selection. For example, any 5 V, < 0.1 W resistor in the control circuit need not be hsted since it is accommodated by nearly all technologies (e.g. as 0806, SMT, PTH, thick film, etc.). For each of the remaining components, all the mechanical package formats should be hsted under the delivery form.

The third step is to strategically group components by delivery form taking into consideration limits on electrical and thermal operating points. This first-cut grouping brings a high level of packaging integration to the system and is a critical step. Similar components from all parts of the circuit become associated.

The fourth step uses the user requirements as constraints along with engineering experience to reassociate components into different groupings. Not all components are easily regrouped. The unassociated components become dominant factors during technology selection. As an example, the high-voltage components of a bootstrap gate-drive supply can be associated with the gate-drive circuit board or the high-voltage power inverter components. Interestingly, most unassociated components reside at the interfaces between functional blocks (as shown in Figure 35.1).

The fifth step is to map the groupings of components to the packaging technologies. This was partially performed in the previous step as engineering judgment guided the regrouping. Refinement of the selection comes when the unassociated components are incorporated. Steps four and five become iterative to provide optimum partition(s).

35.4 Assessing Partitioning Technologies

To better understand the correlation between electrical and physical circuits (partitioning and packaging), consider the morphology of a generic circuit. A circuit has three partitions: components, topologies and controls. Components are active or passive, such as ICs or heat sinks. Topologies are the positioning of the components to provide a function, such as a Buck converter or the thermal structure of silicon soldered on copper clad to ceramic. Controls provide a preferred set of rules for operation of those components, such as voltage regulation or a thermostatically controlled fan. Hence, a circuit design involves electrical and physical design. The physical design is packaging and can be defined as

.. .the art (design) of arranging components to provide a function or characteristic

Note that packaging is a design function, whereas manufacturing embodies the processes to fabricate the designed arrangement. Although packaging and manufacturing are strongly interrelated, they are not synonymous.

The term physical should be further defined. Electrical identifies the form of energy being processed. Hence, physical represents other forms, such as mechanical, thermal, chemical, photonic, etc. The power electronics designer is mostly interested in electric, magnetic, mechanical and thermal. Discussion will be limited to these four energy forms.

An integrated design problem example relating the four energy forms of interest is as follows. A high-frequency magnetic core couples the radiated field into a copper conductor on a PWB and causes eddy current heating, increasing the skin-effect resistance. Higher resistance loss further increases conductor heating which increases the mechanical stresses between the conductor and PWB leading to early failure. Who would notice the problem first? The electrical designer through circuit loss measurements; the thermal designer through a thermograph of that specific spot, or the packaging engineer who first notices the conductors are lifting off the board and assumes the conductor adhesion is poor because of faulty chemistry?

35.4.1 Levels of Packaging

The levels of packaging divides a system, top-down, into lower and lower subassembhes with the boundary drawn between assembly and subassemblies as shown in Fig. 35.2.

1. the boundary conditions of electrical/mechanical/ thermal performance characteristics within the level,

2. The electrical/mechanical/thermal interconnection between each level.

Each level is defined and numbered, bottom-up, in a micro-to-macro manner. Three traditional levels in electronic packaging [3] are also applicable to power packaging. Note that levels are not easily defined. Some packages may be categorized in either of two levels depending on the apphcation.

Level-0: Component(s). This is the base level for a component that a designer can obtain and may be a passive, discrete semiconductor or integrated circuit, including a smart power circuit. The semiconductors and ICs are typically silicon (Si), though there is signifi-

Level 1: Component(s) in Package. (Module)

Level 2: Packagi on Board

Level 3: Board in Rack

FIGURE 35.2 Levels of packaging.

cant development in SiC and GaAs for higher operating temperature and speed.

Level-1: Component(s) in Package. This is basic component packaging. Examples include mount-down and lead-attach of a component or semiconductor in a discrete package, or multiple components in a module. Traditional chip and wire hybrid circuits mounted in a housing (often hermetic) are Level-1 packages. The package provides a self contained environment that aUows the components to be tested, transported and used at the next higher level of packaging while buffering electrical, mechanical and chemical discontinuities from the next level. This package becomes a subassembly to the next higher level.

Level-2: Package on Board. These boards carry mixed-technology components (capacitors, resistors, inductors and packaged discretes) that are usually coated and terminated with a connector. Examples are PCB, IMS (insulated metal substrate) and SMT boards. They differ from Level-1 in the lesser sophistication in fabrication. The board provides a functional partition and is a subassembly to the next packaging level. Level-1.5 {half-level): Chip on Board (COB). This mounts chip and wire semiconductors directly to a PCB or on IMS. A driver in packaging is to combine levels. An objective of the road map wiU be the development of a direction to combine levels.

Level-3: Board in Rack or Sub-Assembly Level. At this level the rack or case is considered. Each board or module is a subassembly connected to a rack backplane, motherboard or free-wired together. An example is the output modules in a multioutput power supply. The sub-module approach provides flexibility and fast assembly time.

Definition of levels can continue into Level-4: Rack in Cabinet and Level-5: Cabinet in Room or Multiple Cabinet Level. The technical issues and methods to partition the product applies to all these levels. Producers and suppliers have business thrusts that are aligned along one or more packaging levels. Note, that combining levels, as done with Levels 1 and 2, is of great advantage.

35.4.2 Technologies

The delivery form, i.e. mechanical support structure for integrating functions, divides the technologies. The simplest delivery form is a monomaterial approach, such as a sihcon integrated circuit. Here, several functions are incorporated into the sihcon. A thick-film hybrid uses ceramic-glass structures to create functions. A glass-epoxy board (FR-4) aUows attachment of discrete components to integrate functions. Remember that the functions are not restricted to electrical, but may include magnetic, mechanical and thermal.

The delivery form is an important aspect since the size of mounted components greatly limits the choices in technologies. The greater the mass of the components, the more mechanically robust the technology needs to be. The technologies reviewed below belong to packaging Level-0 through Level-2 and, generally, sequentially range from fully imbedded components as in sihcon ICs to modestly robust for surface mounted components, to very robust for clamped, screwed and axially leaded. The transition from plated through holes (PTH) to surface mount technology (SMT) occurs within FR-4 and partly explains the greater acceptance of this versatile technology.

Semiconductor Power Integrated Circuits. This is considerably different than the remaining packaging technologies in that it approaches a monomaterial system. Multiple functions can be produced in one material, usually sihcon. This is expanded in the foUowing section. Thick-Film on Ceramic (TEC). Glass based pastes or inks are loaded with electrically conductive materials, such as copper, gold or silver, to form interconnects, loaded with resistive materials to form components, or used unloaded as dielectrics. The pastes are screen printed on ceramic and fired at ~900°C. Vias are formed as holes in dielectric layers and discrete components are surface mounted with solder or adhesives. Only two types of air-fired thick film are considered here: multilayer thick film (TF-multilayer) for control circuitry and thick thick film (TTF) where silver is printed to form up to 160 im conductors for power.

Си Plated on Ceramic (CuPC). Patterns are imaged or transferred to the surface of ceramic. Copper is then plated to a thickness < 125 im (5 mils). Discrete components are attached or fuU thick-film processing is placed on the plated copper with screen-printed components imbedded or discrete components attached. Glass-epoxy with surface mount pads (FR-4, SMT). A fiberglass mesh is impregnated with epoxy and metalized with copper. Interconnect patterns are etched into the foil. The patterned copper clad mesh can be laminated and vias formed by driUed and plated holes. Chip components are surface mounted with solder attachment or conductive polymer. Components can also be imbedded using loaded polymers similar to the TEC process, but with low temperature curing (SMT is surface mount technol-

Insulated Metal Substrate-polymer on Metal (IMS-PM). A polymer is used to isolate and attach a conductive interconnect to a metal plate which provides mechanical support. Vias can be placed between the interconnect and plate, and a layer of polymer and interconnect can be attached to the interconnect layer. Insulated Metal Substratate-steel corded (IMS-PS). A high temperature glass (~900°C) coats a steel plate and a thick

film conductive cermet interconnect is applied upon the glass. The structure is similar to traditional thick film. Vias are processed as in multilayer thick-film. Direct Bonded Copper (DBC). Copper foil is applied to ceramic, bonded at ~ 1063°C, and a pattern is etched. Discrete components are surface mounted with solder or adhesive. There are no vias.

Glass-Epoxy with plated through holes (FR-4, PTH). Same as FR-4 above except leaded components are solder attached with leads placed through holes (PTH is plated through holes ).

Molded Interconnect Device (MID). A high temperature plastic or polymer structure hosting electrical interconnects is fabricated by 1-shot, 2-shot or insert molding. The interconnections are formed by hot-stamping copper foil, imaging and metal plating the polymer, or insert-molding of structured metal. MID lends itself to high volume, 3D, net shape packaging and is extensively overlooked in the power electronics area (excluding automotive). Components can be surface mounted or through-hole with moderate to course line resolution. Only hot embossing is considered here.

Laminated Bus-Bar. A polymer, such as epoxy, glues together thick conductor bars while providing electrical isolation. The bars can be free-floating laminated interconnects or, if sufficiently thick, be the metal carrier. Vias between layers are metal posts or fasteners placed through drilled or stamped holes. These are used in high current systems and can accommodate very large components. These were not considered in this development.

35.4.3 Semiconductor Power Integrated Circuits

As noted in the introduction, the term smart power has been used for several decades to describe the imbedding of control into power processing systems. One approach integrates control and power into a monolithic circuit, such as silicon, and takes on two forms. One is the integration of analog and digital circuitry with discrete power devices. The second apphes to high voltage ICs used for power monitoring and fault control. The term smart power has become synonymous with power integrated circuits (Power ICs) or apphcation specific power ICs (Power ASICs). Motorola trademarked the term SMARTpower circa 1980.

A designer typically is a user of power ICs and seldom influences the chip design. Systems partitioning, as described throughout this chapter, is not directly applicable. However, once the chip is available, the designer is armed with a more functionally integrated component. A background to power ICs is given below to aid the designer in better understanding the technology. An excellent reference noting the beginning of high voltage ICs is an IEEE Press Book by B. J. Baliga [4].

TABLE 35.2 Examples of power ICs (smart power)

Power ICs can be divided into four groups resulting from a matrix of low and high voltage, and low and high current capabilities as identified in Table 35.2. The low-voltage, low-current ICs are readily available for the control and monitoring of power processing functions. These smart chips control power supphes, battery chargers, motor drives, etc., and are often referred to as power controllers. These chips are produced from standard 1С processes and limited to the voltages of the process. Cost follows typical 1С cost structures.

Low-voltage, low-current ICs can be further subdivided into dedicated and programmable chips. In the late 1990s and early 2000s, the incorporation of imbedded control expanded the definition of power controllers. Sophisticated control algorithms that were implemented in digital signal processors (DSPs) were incorporated into programmable power controllers. The role of the power electronics designer further changed to become adept at high performance programming.

Low-voltage, high-current power ICs again use standard 1С processes for fabrication. The higher current requirement is met by creating effectively large device areas that maintain current densities consistent with process characteristics. In the 1970s and 1980s bipolar processing was dominant and large area devices were fabricated. Typically, processes were limited to 40 V and pushed to 60 V for actuator and transistor driver applications. As a side note, the most successful power MOSFET (metal-oxide semiconductor FET) driver in the 1980s used a commercially available digital hne driver 1С. Driver chips were later developed with FET processes that paralleled many low-power FET cells. Again, the required area was determined by the maximum current density of the allowed process.

Dedicated chips of the 1990s used power MOSFET technology to create driver and actuator chips. Apphcations of the low-voltage, high-current ICs fall mostly in the areas of power conditioning for photovoltaic systems, actuators for computer hard drives, actuators and motor drives for automotive and appliance applications, and driver applications in power semiconductors circuits.

Since most all 1С technology was created for computer and telecommunications applications, creation of higher voltage ICs for power was slow to develop. Lack of market size in power did not support substantial technology development, but rather incremental product development. However, high-voltage ICs were developed early on for the gas-tube display market (circa. 1980s). Other significant developments slowly

NMOS ! PMOS

SGS I S G S

4 л./

FIGURE 35.3 Junction isolation used to separate devices or circuits.

occurred, mostly in drivers for power-bridge circuits as used in motor drives and application specific ICs.

Fiigh-voltage ICs are processed with either dielectric isolation or junction isolation. In the 1980s dielectric isolation was used extensively by Dionics Incorporated for display drivers, which had ratings of several hundred volts. Dielectric isolation utilizes silicon dioxide weUs. Devices, such as bipolar transistors, are fabricated in the weUs, which serve as functional islands. The devices are then interconnected at the surface.

Limitation of the dielectric isolation process is the higher cost. FLowever, dielectric isolation does provide for more reliable isolation with greater circuit flexibility. Both power rating and current capacity are low relative to junction isolation because of the planar nature of the structure and interconnects.

Junction isolation became the preferred method starting in mid 1990s with developments from General Electric and FLarris companies foUowed by power ASICs from power semiconductor manufacturers. The isolation method used multiple levels of p-n junctions to form wells. A cross section of several basic technologies is shown in Fig. 35.3. Note the p-type sinkers connecting to the p-material of the substrate to provide ceU isolation. There is also a combination of structures used to produce a BiCMOS process. The CMOS provides the control circuitry while the bipolar structures provide high current-density transistors for power processing.

Junction isolation has several limitations, most significant of which is possible layer inversion. Inversion occurs when the reference substrate, or portions thereof, become reverse biased. Relatively large currents can flow and biasing of four layer structures can cause latch-up. Manufacturers have paid significant attention to minimizing this problem. FLowever, designers must always be cautious that a fault condition or capacitive current from a high-frequency transient does not induce an inversion.

35.5 Full-Cost Model [5]

This is the one issue seldom discussed in the open literature, yet is the greatest driver to selection of circuit design approaches and determination of partitions. Unfortunately, a designer often limits cost estimation to only component cost, i.e. the biU of materials (BOM). The greatest cost is often not

the component, but the handling, mounting, and testing of a component. An exceUent example is the selection of output filter capacitors in dc-dc supphes. The use of a multitude of smaUer ceramic chip capacitors, which can be automatically surfaced mounted, is often less expensive than larger electrolytic through-hole-mounted capacitors, and provide much greater reliabUity over time. (This only apphes to larger volume production.)

The use of cost is also dependent on the positioning product design within the company. A vertically structured design company with captive manufacturing has the advantage of increasing volume by modularizing their circuits to be used across several product lines. Regardless, the foUowing procedure applies for both captive and out-sourced manufacturing.

When discussing cost it is necessary to define centers of cost for both product and business. The terms are defined as foUows.

1. Materials cost represent direct costs of packaging, and include the minimum packaged component (e.g. sihcon chip), component packaging materials (e.g. plastic housing on a TO-220) and packaging materials for manufacture (e.g. solder or adhesives for mount down). If the manufacturer can mount bare die, then these quantities are determined separately. If manufacturing is out-sourced, then the pre-packaged component cost accounts for the first two costs and the manufacturer (or assembler) determines the third cost. The variation in cost by volume must also be included. Volume dependency is greatest for custom products at low volume and lowest for standard high volume products. A typical volume cost factor is 20% decrease in cost per 10-fold increase in volume.

2. Production cost includes factors for wages and product volume, but is independent of material costs, (which is not often assumed when assessing overhead). Production cost can be characterized as a function of technology and quantity. To reflect this into a design tool, it is necessary to describe production cost as a function of simple information, such as the number of SMD and leaded components, and square inches of substrate board. Assessment is as foUows for captive production:

1. Determine the total wages, equipment and facUity depreciation, and other facUity overhead.

2. Determine the number of production technologies in the facility, both in place and avaUable with minimal extension.

3. Determine technology costs by a ratio of the above two parameters.

4. Add scaling factors for volume dependency.

In Fig. 35.4 relative production costs for various technologies (circa. 1999) are shown for fixed volume. Note that chip &: wire is less expensive than

700%

о

Leaded-manual Power chip & wire

Leaded-auto SMD auto

AssembI tec nolog

FIGURE 35.4 Relative production costs. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance. Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

handling a leaded component and is typical for captive facilities. Included scahng factors in your calculations to give a volume dependency for a highly automated production technology. Depreciation is for production equipment and buildings, whereas other overhead covers the significant cost involved in purchasing, management, production technology, etc. 3. Partitioning cost is incurred for each technology used. From the previous technology descriptions it appears straightforward to choose this technology for these components and those technologies for those components based on technical performance attributes. However, there is a drawback to this partitioning. Each partition adds one circuit to be handled through production with an additional interconnect and assembly process. This means additional incremental costs. Assembhng subcircuits into a product is similar to assembling components on boards and is modeled as cost in wages modified by a different overhead factor. For chip &: wire, costs for protecting (encapsulating) chips are included if necessary.

CO об

FIGURE 35.5 Full cost model for circuit partitioning. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance. Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

Ot er OH -

EH e reciation Wages

roducts/ ear

FIGURE 35.6 Cost variation due to volume. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance. Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

4. Full cost combines material costs and production costs as shown in Fig. 35.5. A minimum-packaged-component system is chosen to highhght the possibility of buying nonpackaged components, but the model is valid for any level of packaging. If there is not a captive circuit fabricator, then the cost is obtained through competitive quotes or experience with the manufacturer. A mixture of in-house and out-sourced costs can be included in the model.

5. Product business cost, i.e. returns on investment for development of one product, is an investment in future payback. The total cash flow from development until end of production determines the business costs for a product.

6. Company business cost, i.e. return on investment for cross products reflects the cost of suboptimization within one single product. The value of reusing the same packaging technologies, designs (diagrams) and even physical circuits (building blocks) across different products should be measured at the company level. The value of building blocks becomes obvious through savings in repetitive development costs and maintenance of function. Development and maintenance costs are saved since the function is only developed once and unilaterally maintained across all products.

The impact of volume on building block cost apphed to three motor drive products is shown in Fig. 35.6. At low volumes the main savings are in development and maintenance costs, while at high volumes only savings in full cost matters. The overall conclusion is that, if a partition is necessary to meet requirements, then the partition must be guided by strategic choices in order to optimize cost on a company business level and relative cost diagrams should be used only for optimizing within partitions.

35.6 Partitioning Approach

There are several natural aids to partitioning. Rank ordering common packaging technologies by technical performance (for power processing) also orders most other attributes. As one moves down the list of technologies as described in Section 35.4.2, one finds, in general, increasing electrical performance in current-carrying capacity, decreasing performance in voltage isolation and operating frequency, lower thermal performance and density, less sophisticated processing, and lower cost for lower volumes (except for MID). These monotonic trends aUow rich engineering judgment to effectively group components (step 4 in Section 35.3.1) for optimized partitioning. Important physical characteristics for relevant materials are given in Table 35.3 and Table 35.4.

Following a sequence of first matching the most chaUenging component grouping with the higher performance technology can minimize iterations of the last two steps in Section 35.3.1. The next chaUenging grouping is matched with the next technology of lower, but suitable performance and lowest

TABLE 35.3 Conductor/metal properties

ac aging & roduction costas

ac aging erormance-(electrical, t ermal, mec anical)

TABLE 35.4 Insulator/substrate properties

Functional integration it in tec nolog

0.8 - 0.6

0.4

0.

0 5 0 Surace ensit

FIGURE 35.7 Cost variation within technologies. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance, Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

cost. Starting with the highest performance technology also aUows much lower component groupings to be considered for inclusion at possibly no increased cost. For example, if ceramic thick film is used for chip and wire power die and current sense resistors, the inclusion of thick-film control circuits comes with little added real estate (cost).

The selection of technologies has been very misunderstood because a typical perspective is to look at substrate area cost. The famous doUars per square inch costing of technologies has been used. This is as limiting as using only a BOM for cost driven decisions. A better understanding is required and is aided by the graphical perspective in Fig. 35.7. It is recommended the curves be viewed right to left (as density decreases). The faUing curves represent relative fuU-cost (Section 35.5) of each technology as area changes. The starting and ending points are the practical limits in the use of the technology at certain densities.

As an example, assume a given circuit is designed with only one technology, such as thick film (TF), and as dense as possible. As board area increases (becoming less dense), components can grow in size (0603 to 0805) with larger interconnect traces. The cost increases, following the curves up and to the left. A point is reached in area that a less costly technology may be suitable, such as SMT FR-4. This other technology would decrease cost for the same area. Fience, cost and density decrease, but performance also decreases. Within a range near maximum density, the higher performance TF technology with added area is stiU less costly. This is due to packaging and production costs, and is often overlooked by designers who look at cost per square area of boards without looking at the fuU-cost model.

A more generahzed set of curves is shown in Figure 35.8. This graph, in essence, is created for a specific production facUity. The circuit designer, or design team, would foUow the steps to partitioning, letting the costs of the technologies drive

ас aging & roduction Costs

ac aging erormance: electrical, t ermal, mec anical

TF& lated Cu

Surace ensit

FIGURE 35.8 Generalized relationship of cost and technology. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance. Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

where partitions are best drawn. Remember that the overall circuit is composed of electric, magnetic, mechanical and thermal circuits.

35.7 Example 2.2 kW Motor Drive Design

A 2.2 kW motor drive, consisting of electronics, motor and pump encased in one housing, is used as an example product. The block diagram of the electronics is shown in Fig. 35.1. For an (planar) electrical-mesh circuit, the physical assembly pattern would closely follow the electrical schematic layout and one packaging technology, such as FR-4, could be used, though not efficiently. The design would then follow a single line up and to the left in Fig. 35.7. Using mixed packaging technologies provides multiple assembly levels and the assembly pattern more closely follows groupings of the physical delivery forms of the components. The steps outlined in Section 35.3.2 are followed to determine the proper partitioning of the system to meet performance requirements and provide maximum business profit. The steps are summarized as:

1. user eequirements,

2. component characterization,

3. component grouping,

4. strategic partitioning with constraints,

5. optimizing within partitions.

35.7.1 User Requirements (constraints)

Many user requirements direct the system design as outlined in Section 35.3.1. However, several requirements place specific

constraints on the packaging of the 2.2 kW drive as noted below:

Mechanical: built-in stainless steel tube with diameter of 65 mm, and short as possible.

Thermal: cooling through tube with non-flow of water at 30°C.

Environment: potting complete electronics inside tube

not allowed

Regulatory: UL, CE

Reliability: 1,000,000 quick start/stop

30,000 maximum gradient start/stop 40,000 h lifetime @ 10°C water

35.7.2 Component Characterization Map

A component characterization map is performed on all the components to identify dominant technical and physical attributes, and is illustrated for part of the circuit as in Table 35.1. In this component characterization map components are hsted for each electrical functional block.

35.7.3 Component Grouping

An overview of possible groupings into packaging partitions is obtained by attaching main components and key attributes to the functional block diagram of Fig. 35.1.

35.7.4 Strategic Partitioning with Constraints

A major constraint is the limited space available (65 mm diameter). This makes it obvious that some miniaturization is very valuable, but what should be miniaturized? Packaging cannot miniaturize leaded components. These components require either through-hole PCB (FR-4, for soldering) or some form of lead frame (MID for welding). Power die are top candidates for miniaturization because the die can be grouped into a power module that is much smaller than discrete power components. Also, high power losses do not allow the same packaging technologies to be used as for leaded components.

The remaining nonpower die and associated components are prime candidates for modularization. Highest value is reached if a building block can be reused across different products. Therefore, as much control circuitry as possible should be integrated without violating the possibility for reuse in other products. For this product, the hne communications bus and motor control circuitry would be excluded, but the control for VDE/inrush and PFC would be integrated together with the driver and all sense resistors. This integrates 82% of all power losses for easier cooling, integrates all power-component-dependent control circuitry, and enables product-independent maintenance and power die optimization.

FR u( yr) FR u(2x um) S( у r A)

Subtrt Tch g

TTF uP(2 yr)

В ( A 20 ) TF

mut yr

FIGURE 35.9 Substrate costs (1999). Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance, Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

FIGURE 35.10 Final module combining several packaging approaches. Reprinted with permission, JB Jacobsen and DC Hopkins, Optimally selecting packaging technologies and circuit partitions based on cost and performance, Applied Power Electronics Conference, New Orleans, LA, February 6-10 2000, ©2000, IEEE, New York.

At this stage there are usually new requirements added for cross-product reuse. This apphcation requires 125° С baseplate temperature.

35.7.5 Optimization within Partitions

Optimization requires choosing optimum technologies to meet cost and performance requirements. In Figure 35.9 relative cost of various substrates is shown together with the cost of suitable production technologies. Note that the substrate cost is for equal substrate area but different performance. For example IMS requires more space for control circuitry than TF multilayer because IMS has only one conductor layer.

Figure 35.9 should be used together with Fig. 35.1, which shows that the module includes both power chip &: wire (PC8cW) and low power control circuitry (SMT). DBC, IMS, TTF and CuPC can accommodate the PC8cW. FR4, IMS, TF multilayer and CuPC can accommodate fine line SMT. This should initially lead to the conclusion that DBC, IMS or TTF should be used for power, excluding CuPC due to cost; and FR4 for control, excluding the others due to cost.

Are aU cost issues taken into account and aU requirements met? Not necessarily. Packaging approaches influences component cost. Power sense resistors, which are typically in SMT form, can be integrated in TF multilayer at near-zero incremental cost. Also, less expensive integrated circuits can be chosen when the packaging approach aUows active trimming of associated components. Besides cost, technical issues limit packaging choices for certain circuit partitions. Reliability and temperature requirement (125°C) rule out FR4.

There are fewer and fewer choices. If power die were available as known good die, then power and control could be combined on one substrate with IMS or CuPC. The IMS has drawbacks, such as lower power cycling capability due to a high TCE and is only a one-layer technology, which means more area and less noise immunity. CuPC has neither of these problems, but due to lack of known good power die was not chosen. Also, CuPC does not allow component integration at the cost indicated in Fig. 35.9. A two-substrate solution was needed.

Power DBC was chosen as the obvious highest performing technology among comparable low cost power substrates. The DBC is soldered onto a low cost copper base for thermal management and extends to form a mounting base for the control substrate.

Multilayer thick film was chosen for control circuitry despite the apparently high substrate cost. In the motor module, this substrate is the optimum cost choice because of high component integration, such as the three buried power current-sense resistors and many printed resistors for accurate active trimming of functions associated with the integrated circuits. Partitioning cost is minimized by combining interconnections of substrates with interconnection to I/O terminals in one technology-heavy wire bonding. This has been possible by designing an MID interconnection component with terminals that are wire bondable on one end and solderable on the other. The resulting module is shown in Fig. 35.10.

Other components, both SMT and leaded, were not best accommodated in the module. Therefore, a two-layer FR4 is chosen as the lowest cost technology suitable for both delivery

forms and used for the module and components. Mechanical stability and cooling is achieved by using a patented structure of extruded aluminum profiles.

Using bare die, higher cost substrates and partitioning with different technologies allows the product to surpass cost targets. The partitioning in packaging Levels-1 and -2 address optimization of product business cost as defined in Section 35.5. Designing the module building block as a component for reuse across other products increases volume and reduces cost. More importantly, relative low volume products can benefit from the building block by faster development cycles, lower development cost, lower Level-3 packaging cost and lower maintenance cost. The building block value addresses optimization of company business cost.

Acknowledgment

The author wishes to thank Mr. John B. Jacobsen, Technical Manager, Electronic Engineering and Packaging Department

of Grundfos A/S, Denmark, for supplying all of the apphcation data and module design.

References

1. M. Meinhardt et al, (1999) STATPEP-current status of power electronics packaging for power supplies - methodology, Proc. 14th Annual Applied Power Electronics Conference and Exposition, March 14-18, 1999, IEEE, New York, pp. 16-22.

2. D. C. Hopkins et al. (1998) A framework for developing power electronics packaging, Proc. 14th Annual Power Electronics Conference and Exposition, February 15-19, 1998, IEEE, New York, pp. 9-15.

3. R. R. Tummala and E. J. Rymaszewski (1989) Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York.

4. B. J. Baliga (ed.), (1988) High Voltage Integrated Circuits, IEEE Press, New York.

5. J. B. Jacobsen and D. C. Hopkins (2000) Optimally selecting packaging technologies and circuit partitions based on cost and performance. Applied Power Electronics Conference, New Orleans, LA, February 6-10, 2000, IEEE, New York.